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| E2G0012-17-41 Semiconductor MSM518128/L Semiconductor This version: Jan. 1998 MSM518128/L Previous version: May 1997 131,072-Word 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM518128/L is a 131,072-word 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM518128/L achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM518128/L is available in a 26/24-pin plastic SOJ. The MSM518128L (the low-power version) is specially designed for lower-power applications. FEATURES * 131,072-word 8-bit configuration * Single 5 V power supply, 5% tolerance * Input : TTL compatible, low input capacitance * Output : TTL compatible, 3-state * Refresh : 512 cycles/8 ms, 512 cycles/64 ms (L-version) * Fast page mode, read modify write capability * CAS before RAS refresh, hidden refresh, RAS-only refresh capability * Package: 26/24-pin 300 mil plastic SOJ (SOJ26/24-P-300-1.27) (Product : MSM518128/L-xxJS) xx indicates speed rank. PRODUCT FAMILY Family MSM518128/L-45 MSM518128/L-50 MSM518128/L-60 Access Time (Max.) tRAC tAA tCAC tOEA 45 ns 24 ns 13 ns 13 ns 50 ns 26 ns 14 ns 14 ns 60 ns 30 ns 15 ns 15 ns Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) 90 ns 100 ns 120 ns 682.5 mW 630 mW 525 mW 5.25 mW/ 1.05 mW (L-version) 1/15 Semiconductor PIN CONFIGURATION (TOP VIEW) VSS 1 DQ1 2 DQ2 3 DQ3 4 DQ4 5 WE 6 RAS 8 A0 9 A1 10 A2 11 A3 12 VCC 13 Pin Name A0 - A7, A8R RAS CAS DQ1 - DQ8 OE WE VCC VSS MSM518128/L 26 VSS 25 DQ8 24 DQ7 23 DQ6 22 DQ5 21 CAS 19 OE 18 A8R 17 A7 16 A6 15 A5 14 A4 26/24-Pin Plastic SOJ Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5 V) Ground (0 V) Note: The same GND voltage level must be provided to every VSS pin. 2/15 Semiconductor MSM518128/L BLOCK DIAGRAM RAS CAS Timing Generator Timing Generator 8 Column Address Buffers Internal Address Counter 8 Column Decoders Write Clock Generator WE OE 8 Output Buffers 8 8 A0 - A7 Refresh Control Clock Sense Amplifiers 8 I/O Selector 8 8 DQ1 - DQ8 Input Buffers 8 8 A8R VCC 1 Row Address Buffers 9 Row Decoders Word Drivers Memory Cells On Chip VBB Generator VSS 3/15 Semiconductor MSM518128/L ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 Unit V mA W C C *: Ta = 25C Recommended Operating Conditions Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.75 0 2.4 -1.0 Typ. 5.0 0 -- -- Max. 5.25 0 6.5 0.8 (Ta = 0C to 70C) Unit V V V V Capacitance Parameter Input Capacitance (A0 - A7, A8R) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ8) Symbol CIN1 CIN2 CI/O Typ. -- -- -- (VCC = 5 V 5%, Ta = 25C, f = 1 MHz) Max. 6 7 7 Unit pF pF pF 4/15 Semiconductor DC Characteristics MSM518128/L (VCC = 5 V 5%, Ta = 0C to 70C) Symbol Parameter Output High Voltage Output Low Voltage Input Leakage Current Condition MSM518128 MSM518128 MSM518128 /L-45 /L-50 /L-60 Unit Note Min. Max. VCC 0.4 10 Min. 2.4 0 -10 Max. VCC 0.4 10 Min. 2.4 0 -10 Max. VCC 0.4 10 V V mA 2.4 0 -10 VOH IOH = -5.0 mA VOL IOL = 4.2 mA 0 V VI 6.5 V; ILI All other pins not under test = 0 V DQ disable 0 V VO 5.25 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC -0.2 V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. tRC = 125 ms, ICC10 CAS before RAS, tRAS 1 ms Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (Battery Backup) ILO -10 10 -10 10 -10 10 mA ICC1 -- -- -- -- -- 130 2 1 200 130 -- -- -- -- -- 120 2 1 200 120 -- -- -- -- -- 100 2 1 200 100 mA 1, 2 mA mA 1 1, 5 mA 1, 2 -- 5 -- 5 -- 5 mA 1 -- 130 -- 120 -- 100 mA 1, 2 -- 100 -- 90 -- 80 mA 1, 3 -- 300 -- 300 -- 300 mA 1, 4, 5 Notes : 1. 2. 3. 4. 5. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC - 0.2 V VIH 6.5 V, -1.0 V VIL 0.2 V. L-version. 5/15 Semiconductor AC Characteristics (1/2) MSM518128/L (VCC = 5 V 5%, Ta = 0C to 70C, Input Pulse Levels 0 V to 3 V) Note 1, 2, 3 Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS CAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (L-version) RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS MSM518128 MSM518128 MSM518128 /L-45 /L-50 /L-60 Unit Note Symbol Min. Max. Min. Max. Min. Max. tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH 90 140 34 75 -- -- -- -- -- 0 0 0 3 -- -- 35 45 45 14 10 10 14 45 5 28 17 12 0 7 0 12 35 20 0 0 0 -- -- -- -- 45 14 24 28 14 -- 10 10 50 8 64 -- 10,000 100,000 100 150 36 77 -- -- -- -- -- 0 0 0 3 -- -- 40 50 50 14 10 10 14 50 5 30 18 13 0 8 0 13 40 26 0 0 0 -- -- -- -- 50 14 26 30 14 -- 10 10 50 8 64 -- 10,000 100,000 120 170 40 90 -- -- -- -- -- 0 0 0 3 -- -- 50 60 60 15 10 10 15 60 5 35 20 15 0 10 0 15 50 30 0 0 0 -- -- -- -- 60 15 30 35 15 -- 10 10 50 8 64 -- 10,000 100,000 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 5 6 4, 5, 6 4, 5 4, 6 4 4 4 7 7 3 -- -- -- 10,000 -- -- -- 31 21 -- -- -- -- -- -- -- -- -- -- -- -- 10,000 -- -- -- 36 24 -- -- -- -- -- -- -- -- -- -- -- -- 10,000 -- -- -- 45 30 -- -- -- -- -- -- -- -- -- 6/15 Semiconductor AC Characteristics (2/2) MSM518128/L (VCC = 5 V 5%, Ta = 0C to 70C, Input Pulse Levels 0 V to 3 V) Note 1, 2, 3 Parameter Write Command Set-up Time Write Command Hold Time Write Command Hold Time from RAS Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) Symbol MSM518128 MSM518128 MSM518128 /L-45 /L-50 /L-60 Unit Note Min. Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0 13 40 10 13 14 14 0 13 40 13 38 52 75 53 0 10 25 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min. 0 15 50 10 15 15 15 0 15 50 15 50 60 85 60 0 10 30 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 10 10 9 0 12 35 10 12 14 14 0 12 35 12 36 48 70 50 0 10 25 tWCS tWCH tWCR tWP tOEH tRWL tCWL tDS tDH tDHR tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR 7/15 Semiconductor Notes: MSM518128/L 1. A start-up delay of 200 s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 50 pF. The output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 8/15 E2G0092-17-41E Semiconductor MSM518128/L ,,, , ,,,, TIMING WAVEFORM Read Cycle tRC tRAS tRP RAS VIH - VIL - tAR tCRP tCRP tCSH tRCD VIH - CAS VIL - VIH - VIL - VIH - VIL - VIH - VIL - VOH - tRAD tRSH tCAS tRAL tASR tRAH tASC tCAH Address Row Column tRCS tRRH tRCH WE OE tAA tROH tOEA tRAC tCAC tOEZ tOFF DQ VOL - Open Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRAS tRP RAS VIH - VIL - VIH - VIL - tAR tCRP tCRP tCSH tRCD tRSH CAS tRAD tRAH tCAS tASR tASC tCAH tRAL Address VIH - VIL - VIH - Row Column tWCS tWCH tWP tCWL WE VIL - VIH - tWCR tRWL OE VIL - VIH - tDS tDHR tDH DQ VIL - Valid Data-in Open "H" or "L" 9/15 ,,, Semiconductor MSM518128/L Read Modify Write Cycle tRWC tRAS tRP RAS VIH - VIL - tAR tCSH tCRP tCRP tRCD tRSH VIH - CAS VIL - tCAS tASR tRAH tASC tCAH VIH - Address VIL - WE OE VIH - VIL - VIH - VIL - VI/OH- Row Column tRAD tRWD tCWD tAA tAWD tCWL tRWL tWP tRCS tOEA tOED tOEH tCAC tRAC tOEZ tDS tDH DQ VI/OL- tCLZ Valid Data-out Valid Data-in "H" or "L" 10/15 , ,, , , ,, Semiconductor MSM518128/L Fast Page Mode Read Cycle tRASP tRP VIH - RAS V - IL VIH - CAS VIL - VIH - VIL - VIH - VIL - tAR tRHCP tCRP tRCD tPC tRSH tCRP tCP tCP tRAD tCAS tCAS tCAS tASR tRAH tASC tCSH tCAH tASC tCAH tASC tRAL tCAH Address Row Column Column Column tRCS tRCH tRCS tAA tRCH tRCS tAA tRCH WE tAA tRRH VIH - OE VIL - tOEA tCPA tCPA tOEA tOEA tCAC tRAC tOFF tOEZ tCAC tOFF tCAC tOFF tCLZ tOEZ tCLZ tOEZ VOH - DQ VOL - tCLZ Valid Data-out Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP tPC tRP VIH - RAS V - IL VIH - CAS VIL - VIH - VIL - tAR tRHCP tCRP tRCD tRSH tCRP tCAS tCP tCP tCAS tCAS tASR tRAH tASC tRAD tCSH tCAH tASC tCAH tASC tCAH tRAL Address Row tWCS VIH - WE VIL - Column tCWL tWCH tWP tWCR tDH Column tCWL tWCS tWCH tWP Column tRWL tCWL tWCS tWCH tWP tDS tDH tDS tDS tDH DQ VIH - VIL - Valid Data-in Valid Data-in Valid Data-in tDHR Note: OE = "H" or "L" "H" or "L" 11/15 Semiconductor Fast Page Mode Read Modify Write Cycle VIH - RAS VIL - tAR VIH - CAS VIL - Address VIH - VIL - V WE IH - VIL - VIH - OE V - IL VI/OH- VI/OL - DQ RAS-Only Refresh Cycle RAS VIH - VIL - CAS VIH - VIL - Address VIH - VIL - DQ VOH - VOL - ,,,, , , , tRASP tRP tCSH tPRWC tRCD tCAS tCP tCAS tCP tRSH tCAS tCRP tRAD tRAH tCAH tASC tASC tASR tASC tCAH tCAH tRAL Row Column tRWD Column Column tRCS tCWD tCWL tRCS tCPWD tCWD tAWD tCWL tRCS tCPWD tCWD tAWD tRWL tCWL tAWD tRAC tDS tWP tDH tDS tWP tDH tROH tDS tWP tDH tAA tCPA tAA tCPA tAA tOEA tOEA tOEA tOED tOED tOED tCAC tOEZ tCAC tOEZ In MSM518128/L tCAC tOEZ Out In Out Out In tCLZ tCLZ tCLZ "H" or "L" tRC tRAS tRP tCRP tRPC tASR tRAH Row tOFF Open Note: WE, OE = "H" or "L" "H" or "L" 12/15 ,, ,,, Semiconductor MSM518128/L CAS before RAS Refresh Cycle tRC tRP tRAS tRP RAS VIH - VIL - tRPC tRPC tCP tCSR tCHR CAS VIH - VIL - VOH - VOL - tOFF DQ Open Note: WE, OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC tRC tRAS tRP tRAS tRP RAS VIH - - tAR VIL tCRP tRCD tRSH tCHR CAS VIH - VIL - tASR tRAD tASC tRAH tCAH Address VIH - VIL - Row Column tRCS tRAL tRRH VIH - WE V IL - VIH - OE V IL - tAA tROH tOEA tRAC DQ VOH - VOL - tCAC tCLZ Valid Data-out tOFF tOEZ "H" or "L" 13/15 ,,, , Semiconductor MSM518128/L Hidden Refresh Write Cycle tRC tRC tRAS tRP tRAS tRP RAS VIH - VIL - VIH - tAR tCRP tRCD tRSH tCHR CAS VIL - tASR tRAD tASC tRAH tCAH t RAL Address VIH - VIL - Row Column tWCS tWCH VIH - WE V IL - VIH - OE V IL - tWP tWCR tDS tDH V- DQ IH VIL - Valid Data-in tDHR "H" or "L" 14/15 Semiconductor MSM518128/L PACKAGE DIMENSIONS (Unit : mm) SOJ26/24-P-300-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.80 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/15 |
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